FPGA-DSP Board for Narrowband SDR

When the push-to-talk (PTT) signal on header K7 is pulled logic Low (see Part 1, Figure 2), the FPGA goes into transmit mode. A CW carrier can then be generated with the DDS block in the FPGA, through the DAC, by pulling the KEY signal Low.

In addition, the Weaver blocks are implemented in such a way that they can be used “backwards” to form an SSB modulator. When USB or LSB is selected and PTT pulled Low, the audio at the microphone input is sampled, compressed and low-pass filtered, and then fed to the modulator. This works very well, but needs external filtering due to the difficulty of up-sampling from the low KSPS rates in the audio and modulator to the high 120 MSPS rate used by the DAC. The two spectrum plots in Figure 1 show transmitter signals generated in the 14 MHz (20-m) amateur radio band. The graph on the left is a CW signal generated directly by the DDS. The discrete noise components, spurious responses or “spurs”, around the carrier are around −70 dBc (i.e. they have an amplitude of −70 dB relative to the carrier) and originate from clock signals inside the FPGA. This signal may be amplified to, say, 5 to 10 watts and transmitted while keeping interference risks low.

The spectrum on the right of Figure 1 shows the output from the Weaver SSB modulator when fed with an audio signal. Here the internal clock signal residues are much stronger, and strong alias products due to the modulation are visible too. With these unwanted signal components now as strong as −30 dBc, one should not simply amplify and transmit; filtering is required.

Apart from the spurious/alias products from the modulator there are also other limitations to be aware of. These stem mainly from the fact that the non-modulated signals generated by the FPGA through the DAC are not as clean as one would want ideally. This has two reasons mainly:
1. The clock for the DAC, generated at 240 MHz and then divided by two, is created by the internal PLL circuitry of the FPGA. This master PLL clock signal is not ideal with respect to phase noise, i.e. its output has a certain amount of jitter and is not a perfect square wave with an exactly determined frequency and phase.
2. There will also be discrete spurious frefilquency components in the output. These have different origins, like unwanted coupling between different clocks, or quantization effects in the DDS blocks and lookup tables due to word-size limitations in calculation steps, memory and DAC resolution. Some of these parasite signals are visible in the unmodulated spectrum in Figure 1 (left graph).

fig 1 3 FPGA DSP Board for Narrowband SDR

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07. February 2019 by sam
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